Core engineering and protocols for Single-Cycle Violation Handling.
When a security breach or rogue bus access occurs, relying on software interrupt service routines (ISRs) introduces thousands of clock cycles of latency—more than enough time for an attacker's DMA burst transfer to exfiltrate critical key material. EmbeddedWall operates purely in hardware logic at the bus transaction clock rate.
Upon detecting an illegal bus transaction, EmbeddedWall instantly terminates the bus cycle with an AXI SLVERR or DECERR response, discarding the data. If multiple unauthorized attempts occur in rapid succession, the firewall controller escalates defensively: it halts the offending peripheral master, issues a high-priority Non-Maskable Interrupt (NMI) to the secure core, and can trigger automated zeroization of sensitive cryptographic buffers.